What Is the Difference Between an 8051, 8052, 8031, 8032, 80C320, and an E5?

Many designers are familiar with the 8-bit microcontroller architecture called the 8051, originally introduced by Intel. Today, the 8051 architecture is still popular and employed in thousands of embedded applications. Variations of the 8051 architecture are produced by Triscend, Intel, Atmel, Philips, Infineon (Siemens), ISSI, and Cygnal, to name a few.

The 8052 is a super-set of the original 8051. It added 128 more bytes of internal RAM and another 16-bit timer, for a total of three counters.

The 8051 executes code from an embedded masked ROM. An 8751 is similar, but executes code from internal EPROM. There is also ROM-less version that executes code from external memory, called the 8031. Architecturally, the 8051 and 8031 are nearly identical. However, because the 8051 executes code from internal ROM, the 8051 has two more byte-wide programmable I/O (PIO) ports than the 8031. The 8031 loses those two PIO ports for connecting to external memory

Like the 8051, the 8052 executes from masked ROM while the 8752 executes from internal EPROM. There is a ROM-less version called the 8032. See Table 1.

Table 1. 8051 Part Numbering.

Base Architecture	Code Executes From …
Base Architecture	Mask ROM	Internal EPROM	External EPROM/Flash
8051	8051	8751	8031
8052	8052	8752	8032

The 80C320 is like a ROM-less 8052 but with some significant enhancements. First, the instruction cycle for the original 8051 was 12 clock cycles. The 80C320 reduced the instruction to only 4 clock cycles, roughly tripling overall performance. The 80C320 also added a second serial port, a watchdog timer, a second data pointer, and a variable-speed MOVX (move to external data) instruction.

Figure 1. Triscend E5 Block Diagram.

The embedded 8051-compatible microcontroller within an E5 device is similar to the 80C320 and has similar performance. Some of the major Triscend E5 enhancements, shown in Figure 1, include the following.

· Additional XDATA RAM, from 8K-bytes to 40K-bytes on chip

· A glueless memory interface to standard byte-wide Flash

· Glueless code banking to support up to 2M-bytes of application code (requires code-banking compiler like Keil)

· A two-channel DMA controller, supporting up to 40M-byte per second data transfers

· An embedded high-performance bus coupled with power programmable logic, allowing you to add your own custom peripheral set or interface logic

· Programmable wait-state circuitry provides flexible peripheral timing

· Up to 150 user-defined I/O pins

· Embedded JTAG port and hardware breakpoint unit for easy in-system debugging, eliminating the need for an in-circuit emulator

Furthermore, the embedded programmable logic—called CSL—on an E5 allows you to build your own custom peripheral set. Need more timers and UARTs? No problem, drag-and-drop a few from the FastChip library into your design. Need completely custom logic? Again, no problem. Use schematic capture or logic synthesis to create the exact function required in your application. Table 2 compares the E5 against other 8051-based devices.

Table 2. Differences Between Various 8051-Based Devices.

	8051	8052	80C320	E5
Clocks per instruction cycle (fewer is better)	12	12	4	4
Timers	2	3	3	3 plus using CSL
Watchdog Timer	No	No	Yes	Yes
UARTs/serial ports	1	1	2	1 plus using CSL
Internal DATA RAM bytes	128	256	256	256
Internal XDATA RAM bytes	0	0	0	8K to 40K, depending on device
Maximum program size without external logic	64K	64K	64K	2M 16M with effort
Wait-state support	No	No	Some capability with variable-speed MOVX instruction	Yes
DMA channels	0	0	0	2
Maximum PIO port pins	32	32	16	Up to 150, depending on package
Debug without emulator	No	No	No	Yes, uses embedded JTAG port
Number of interrupts	Fixed	Fixed	Fixed	Expandable via CSL

For more information on the Triscend E5 family, visit the following web link.

http://www.triscend.com/products/IndexE5.html