Steven K. Knapp
Steve's broad, multidisciplinary experience produced results across a range of technologies and businesses. The following links provide a sample.
- Technical Writing
- User Guides
- Data Sheets
- Articles
- Software Development
- Intellectual Property (IP) Core Development
- Customer Support Infrastructure Development
- Hardware Development Boards and Platforms
- Patents
User Guides
SiliconBlue iCEman65 Evaluation Kit User Guide
Xilinx Spartan-3AN In-System Flash User Guide
Xilinx Spartan-3 Generation Configuration User Guide
Xilinx Spartan-3 Generation FPGA User Guide
- Chapter 3: Using Digital Clock Managers (DCMs)
Chapter 4: Using Block RAM
Xilinx Spartan-3A Starter Kit Board User Guide
Xilinx Spartan-3E Starter Kit Board User Guide
Xilinx Spartan-3 Starter Kit Board User Guide
Xilinx PicoBlaze 8-bit Embedded Microcontroller User Guide
Xilinx LogiCore PCI Master and Slave Interface User's Guide
Data Sheets
Steve created the following data sheets including most of the technical illustrations
SiliconBlue iCE65 Ultra-Low Power Programmable Logic Family
SiliconBlue iCE65L04 DiCE Data Sheet
SiliconBlue iCE65L08 DiCE Data Sheet
Xilinx Spartan-3AN FPGA Family Data Sheet
Xilinx Spartan-3A FPGA Family Data Sheet
Xilinx Spartan-3E FPGA Family Data Sheet
Xilinx Spartan-3 FPGA Family Data Sheet
Triscend A7S Configurable System-on-Chip Platform (ARM7TDMI)
Triscend E5 Configurable System-on-Chip Platform (8051/8052)
Development/Evaluation Boards
Steve specified and, in many cases, either developed or documented the following development or evaluation boards.
Application Notes
Xilinx XAPP462: Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs
Xilinx XAPP463: Using Block RAM in Spartan-3 Generation FPGAs
Triscend AN07: Using Keil Development Tools with Triscend FastChip and the E5 CSoC Family
Xilinx XAPP065: XC4000 Series Edge-Triggered and Dual-Port RAM Capability
Xilinx: Fully Compliant PCI Interface in an XC3164A-2 FPGA
Xilinx: A Plug and Play Interface Using Xilinx FPGAs
The next three application notes first appeared as chapters in The Programmable Gate Array Design Handbook, Xilinx, First Edition, 1986.
Xilinx: Ins and Outs of Logic Cell Array I/O Blocks
Xilinx: A Seven-Segment Display Driver
The following application note also appeared in the Intel Memory Design Handbook, 1986.
Intel AP-187: MEGABITS TO MEGABYTES: Bubble Memory System Design and Board Layout
White Papers
Xilinx XC5200 vs. Altera FLEX 8000A FPGAs
XC4000-Series FPGAs: The Best Choice for Delivering Logic Cores
Conference Papers
FPGA Summit 2008: Session organizer for Tutorial 2A: Getting Your FPGA Application Up and Running, author and speaker for "Test Tools and Equipment" portion.
DesignCon 2000: A Configurable System-on-Chip Device Facilitates Customization and Reuse
Custom Integrated Cicuits Conference (CICC 2000): Field Configurable System-on-Chip Device Architecture
Embedded Systems Conference (ESC '99): Rapidly Developing Embedded Systems Using Configurable Processors
Embedded Systems Conference (ESC '98): Configurable Embedded Systems: Using Programmable Logic to Compress Embedded System Design Cycles
Design SuperCon '97: Designing a PCI Target/Initiator in FPGAs
Silicon Valley PC Conference: Using LogiCore Modules for PCI Card Design
Asian EE PLD Conference: Using Programmable Logic to Accelerate DSP Functions
Programmable Logic Breakthrough '95: Hot Applications: PCI, Plug and Play, PCMCIA
Wescon '91: Module Generators for Xilinx Field Programmable Gate Arrays
Wescon '88, Electro '88: Optimizing Programmable Gate Array Designs
Patents
Steve has twelve patents issued to date, with other filings in progress at the U.S. Patent and Trademark Office
- US Patent #5422833: Method and System for Propagating Data Type for Circuit Design from a High Level Block Diagram
- US Patent #5499192: Method for Generating Logic Modules from a High Level Block Diagram
- US Patent #5553001: Method for Optimizing Resource Allocation Starting from a High Level
- US Patent #5574655: Method of Allocating Logic Using General Function Components
- US Patent #5617573: State Splitting for Level Reduction
- US Patent #5737234: Method of Optimizing Resource Allocation Starting from a High Level Block Diagram
- US Patent #6691266: Bus Mastering Debugging System for Integrated Circuits
- US Patent #7243227: Method and Apparatus to Copy Protect Software Programs
- US Patent #7281082: Flexible Scheme for Configuring Programmable Semiconductor Devices Using or Loading Programs from SPI-based Serial Flash Memories that Support Multiple SPI Flash Vendors and Device Families
- US Patent #7358762: Parallel Interface for Configuring Programmable Devices
- US Patent #7454556: Method to Program non-JTAG Attached Devices or Memories Using a PLD and Its Associated JTAG Interface
- US Patent #7535249: Authentication for information provided to an integrated circuit
Web-Based Projects
Triscend Configurable System-on-Chip Learning Center (1998)
Although embarrassing simple by today's standard, this project was one of the early attempts at web-based customer training.
Tutorials
Building a Working Design Example Using the Triscend A7 Evaluation Board
Triscend FastChip 2.3.0 Tutorial for the E5 CSoC Device
Technical Training
Triscend A7 Configurable System-on-Chip Hardware Overview
Triscend FastChip 2.1.2 and A7 Configuration System-on-Chip FAE Training
Triscend E5 Configurable System Interconnect (CSI) Bus
Triscend E5 Configurable System-on-Chip
Articles (by Steven K. Knapp)
XCell Journal (2nd Quarter, 2005):
Implementing New Configuration Options for the Spartan-3E Family
Personal Engineering (Dec. '98):
FPGAs furnish fast, furious FIR filters
Personal Engineering (Oct. '98):
Parallel processing in FPGAs rivals DSP speed
Personal Engineering (July '98):
Constant-coefficient multipliers save FPGA space, time
Personal Engineering (May '98):
FPGA lookup tables build flexible pattern matchers
Personal Engineering (Mar. '98):
Programmable logic overcomes processor bottlenecks
Personal Engineering (Jan. '98):
In HDLs, what you see isn't always what you get
Personal Engineering (Nov. '97):
KISS those asynchronous-logic problems good-bye
Personal Engineering (Sept. '97):
Support options for programmable logic don’t differ much from board design
Personal Engineering (July '97):
Understanding programmable logic means digesting its alphabet soup
Electronic Products & Technology (ep&t) (Sept. '96):
FPGAs Tackle Multimedia, Communications DSP Jobs
Electronic Design (Sept. '90):
Accelerate FPGA Macros with One-Hot Approach
Electronic Engineering Times (EE Times) (May '87):
The Acid Test
Electronic Design (Aug. '85):
Once a difficult task, bubble memory design is now a question of layout
Solutions (Sept./Oct. '85):
Megabits to Megabytes: Bubble Memory System Design and Board Layout
Articles (about Steven K. Knapp)
Customer Support Management (July/Aug. 2000):
Mind Your Own Business
The article describes the Triscend SupportCenter web-based technical support system design and created by Steve Knapp in association with SafeHarbor Technology.
Software Manuals and Guides
Adept Programming Software and ICEUTIL.EXE Installation Guide
Using the Triscend LiteLoader Software
X-BLOX Reference/User Guide
Although Steve did not format or compile the material for this manual, he provided major portions of the material. He was the overall architect and manager for the X-BLOX project.
Although Steve did not format or compile the material for this manual, he provided major portions of the material. He was the overall architect and manager for the X-BLOX project.
Keywords
FPGA, field programmable gate array, programmable logic, CPLD, EPLD, configurable, system-on-chip, SoC, CSoC, embedded, processor, microcontroller, 8051, 8052, 8031, 8032, E5, ARM7, ARM9, ARM7TDMI, FastChip, XACT, ISE, Spartan-3, Spartan-3E, Spartan-3A, Spartan-3AN, iCE65, starter kit, tutorial, bubble memory, Xilinx, Triscend, SiliconBlue, Intel, block RAM, BRAM, DCM, DLL, boards, evaluation kit, patent, X-BLOX, logic synthesis, Flash, SPI, security, configuration, PCI, LogiCore, Plug-n-Play, SupportCenter, IP, intellectual property